CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
10.6 GPIF Synchronous Signals
Figure 17. GPIF Synchronous Signals Timing Diagram[20]
t
IFCLK
IFCLK
t
SGA
GPIFADR[8:0]
RDY
X
t
SRY
t
RYH
DATA(input)
valid
t
SGD
t
DAH
CTLX
t
XCTL
DATA(output)
N
N+1
t
XGD
Table 18. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[20, 21]
Parameter
tIFCLK
Description
Min
20.83
8.9
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
IFCLK Period
tSRY
tRYH
tSGD
tDAH
tSGA
tXGD
tXCTL
RDYX to Clock Setup Time
Clock to RDYX
GPIF Data to Clock Setup Time
GPIF Data Hold Time
9.2
0
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTLX Output Propagation Delay
7.5
11
6.7
Table 19. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[21]
Parameter
tIFCLK
Description
Min.
20.83
2.9
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
IFCLK Period[22]
200
tSRY
tRYH
tSGD
tDAH
tSGA
tXGD
tXCTL
RDYX to Clock Setup Time
Clock to RDYX
3.7
GPIF Data to Clock Setup Time
GPIF Data Hold Time
3.2
4.5
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTLX Output Propagation Delay
11.5
15
10.7
Notes
20. Dashed lines denote signals with programmable polarity.
21. GPIF asynchronous RDY signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK.
x
22. IFCLK must not exceed 48 MHz.
Document #: 38-08032 Rev. *N
Page 42 of 62
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