CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
10.3 Data Memory Read
Figure 13. Data Memory Read Timing Diagram
t
CL
Stretch = 0
CLKOUT[17]
t
t
AV
AV
A[15..0]
t
t
STBH
STBL
RD#
t
SCSL
CS#
OE#
t
SOEL
t
DSU
[19]
t
DH
t
ACC1
D[7..0]
data in
Stretch = 1
t
CL
CLKOUT[17]
t
AV
A[15..0]
RD#
CS#
t
DSU
t
[19]
DH
t
ACC1
D[7..0]
data in
Table 16. Data Memory Read Parameters
Parameter Description
1/CLKOUT Frequency
Min
Typ
20.83
41.66
83.2
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
48 MHz
24 MHz
12 MHz
tCL
tAV
Delay from Clock to Valid Address
Clock to RD LOW
10.7
11
tSTBL
tSTBH
tSCSL
tSOEL
tDSU
tDH
Clock to RD HIGH
11
Clock to CS LOW
13
Clock to OE LOW
11.1
Data Setup to Clock
Data Hold Time
9.6
0
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either
RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which
is based on the stretch value
Note
19. t
and t
are computed from these parameters as follows:
ACC2
ACC2
ACC2
ACC3
ACC3
ACC3
t
t
t
t
(24 MHz) = 3*t – t –t
= 106 ns
(48 MHz) = 3*t – t – t = 43 ns
DSU
CL
AV DSU
CL
AV
(24 MHz) = 5*t – t –t = 190 ns
(48 MHz) = 5*t – t – t = 86 ns.
DSU
CL
AV DSU
CL
AV
Document #: 38-08032 Rev. *N
Page 39 of 62
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