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CY7C68014A-56BAXC 参数 Datasheet PDF下载

CY7C68014A-56BAXC图片预览
型号: CY7C68014A-56BAXC
PDF下载: 下载PDF文件 查看货源
内容描述: EZ- USB FX2LP ™ USB微控制器 [EZ-USB FX2LP⑩ USB Microcontroller]
分类和应用: 总线控制器微控制器和处理器外围集成电路数据传输可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 60 页 / 3344 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号CY7C68014A-56BAXC的Datasheet PDF文件第28页浏览型号CY7C68014A-56BAXC的Datasheet PDF文件第29页浏览型号CY7C68014A-56BAXC的Datasheet PDF文件第30页浏览型号CY7C68014A-56BAXC的Datasheet PDF文件第31页浏览型号CY7C68014A-56BAXC的Datasheet PDF文件第33页浏览型号CY7C68014A-56BAXC的Datasheet PDF文件第34页浏览型号CY7C68014A-56BAXC的Datasheet PDF文件第35页浏览型号CY7C68014A-56BAXC的Datasheet PDF文件第36页  
CY7C68013A/CY7C68014A  
CY7C68015A/CY7C68016A  
Table 5-1. FX2LP Register Summary (continued)  
Hex Size Name  
Description  
b7  
0
b6  
0
b5  
b4  
b3  
b2  
b1  
0
b0  
Default  
Access  
E6A4 1  
E6A5 1  
E6A6 1  
E6A7 1  
E6A8 1  
E6A9 1  
E6AA 1  
E6AB 1  
E6AC 1  
E6AD 1  
E6AE 1  
E6AF 1  
E6B0 1  
E6B1 1  
E6B2 1  
E6B3 1  
E6B4 1  
E6B5 1  
EP4CS  
Endpoint 4 Control and  
Status  
NPAK1  
NPAK0  
FULL  
EMPTY  
STALL  
00101000 rrrrrrrb  
00000100 rrrrrrrb  
00000100 rrrrrrrb  
00000010 R  
EP6CS  
Endpoint 6 Control and  
Status  
0
NPAK2  
NPAK1  
NPAK0  
FULL  
FULL  
0
EMPTY  
EMPTY  
PF  
0
STALL  
STALL  
FF  
EP8CS  
Endpoint 8 Control and  
Status  
0
0
NPAK1  
NPAK0  
0
0
EP2FIFOFLGS  
EP4FIFOFLGS  
EP6FIFOFLGS  
EP8FIFOFLGS  
EP2FIFOBCH  
EP2FIFOBCL  
EP4FIFOBCH  
EP4FIFOBCL  
EP6FIFOBCH  
EP6FIFOBCL  
EP8FIFOBCH  
EP8FIFOBCL  
SUDPTRH  
Endpoint 2 slave FIFO  
Flags  
0
0
0
EF  
Endpoint 4 slave FIFO  
Flags  
0
0
0
0
0
PF  
EF  
FF  
00000010 R  
Endpoint 6 slave FIFO  
Flags  
0
0
0
0
0
PF  
EF  
FF  
00000110 R  
Endpoint 8 slave FIFO  
Flags  
0
0
0
0
0
PF  
EF  
FF  
00000110 R  
Endpoint 2 slave FIFO  
total byte count H  
0
0
0
BC12  
BC4  
0
BC11  
BC3  
0
BC10  
BC2  
BC10  
BC2  
BC10  
BC2  
BC10  
BC2  
A10  
A2  
BC9  
BC1  
BC9  
BC1  
BC9  
BC1  
BC9  
BC1  
A9  
BC8  
BC0  
BC8  
BC0  
BC8  
BC0  
BC8  
BC0  
A8  
00000000 R  
Endpoint 2 slave FIFO  
total byte count L  
BC7  
0
BC6  
0
BC5  
0
00000000 R  
Endpoint 4 slave FIFO  
total byte count H  
00000000 R  
Endpoint 4 slave FIFO  
total byte count L  
BC7  
0
BC6  
0
BC5  
0
BC4  
0
BC3  
BC11  
BC3  
0
00000000 R  
Endpoint 6 slave FIFO  
total byte count H  
00000000 R  
Endpoint 6 slave FIFO  
total byte count L  
BC7  
0
BC6  
0
BC5  
0
BC4  
0
00000000 R  
Endpoint 8 slave FIFO  
total byte count H  
00000000 R  
Endpoint 8 slave FIFO  
total byte count L  
BC7  
BC6  
A14  
A6  
0
BC5  
A13  
A5  
0
BC4  
A12  
A4  
0
BC3  
A11  
A3  
00000000 R  
Set-up Data Pointer high A15  
address byte  
xxxxxxxx RW  
xxxxxxx0 bbbbbbbr  
SUDPTRL  
Set-up Data Pointer low A7  
address byte  
A1  
0
SUDPTRCTL  
Set-up Data Pointer Auto  
Mode  
0
0
0
0
SDPAUTO 00000001 RW  
2
reserved  
E6B8 8  
SET-UPDAT  
8 bytes of set-up data  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
xxxxxxxx R  
SET-UPDAT[0] =  
bmRequestType  
SET-UPDAT[1] =  
bmRequest  
SET-UPDAT[2:3] = wVal-  
ue  
SET-UPDAT[4:5] = wInd-  
ex  
SET-UPDAT[6:7] =  
wLength  
GPIF  
E6C0 1  
E6C1 1  
GPIFWFSELECT  
GPIFIDLECS  
Waveform Selector  
SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0  
FIFORD1  
0
FIFORD0  
IDLEDRV  
11100100 RW  
10000000 RW  
GPIF Done, GPIF IDLE DONE  
drive mode  
0
0
0
0
0
E6C2 1  
E6C3 1  
E6C4 1  
E6C5 1  
GPIFIDLECTL  
GPIFCTLCFG  
Inactive Bus, CTL states  
CTL Drive Type  
0
0
CTL5  
CTL5  
0
CTL4  
CTL4  
0
CTL3  
CTL3  
0
CTL2  
CTL2  
0
CTL1  
CTL1  
0
CTL0  
11111111 RW  
00000000 RW  
00000000 RW  
00000000 RW  
TRICTL  
0
0
CTL0  
[11]  
GPIFADRH  
GPIF Address H  
0
GPIFA8  
GPIFA0  
[11]  
GPIFADRL  
GPIF Address L  
GPIFA7  
GPIFA6  
GPIFA5  
GPIFA4  
GPIFA3  
GPIFA2  
GPIFA1  
FLOWSTATE  
FLOWSTATE  
E6C6 1  
Flowstate Enable and  
Selector  
FSE  
0
0
0
0
FS2  
FS1  
FS0  
00000000 brrrrbbb  
E6C7 1  
E6C8 1  
FLOWLOGIC  
Flowstate Logic  
LFUNC1  
CTL0E3  
LFUNC0  
CTL0E2  
TERMA2  
TERMA1  
TERMA0  
CTL3  
TERMB2  
CTL2  
TERMB1  
CTL1  
TERMB0  
CTL0  
00000000 RW  
00000000 RW  
FLOWEQ0CTL  
CTL-Pin States in  
Flowstate  
(when Logic = 0)  
CTL0E1/  
CTL5  
CTL0E0/  
CTL4  
E6C9 1  
E6CA 1  
E6CB 1  
E6CC 1  
FLOWEQ1CTL  
FLOWHOLDOFF  
FLOWSTB  
CTL-Pin States in Flow- CTL0E3  
state (when Logic = 1)  
CTL0E2  
CTL0E1/  
CTL5  
CTL0E0/  
CTL4  
CTL3  
CTL2  
CTL1  
CTL0  
00000000 RW  
00010010 RW  
00100000 RW  
00000001 rrrrrrbb  
Holdoff Configuration  
HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD HOSTATE HOCTL2  
0
HOCTL1  
MSTB1  
FALLING  
HOCTL0  
MSTB0  
RISING  
Flowstate Strobe  
Configuration  
SLAVE  
RDYASYNC CTLTOGL  
SUSTAIN  
0
MSTB2  
FLOWSTBEDGE  
Flowstate Rising/Falling  
Edge Configuration  
0
0
0
0
0
0
E6CD 1  
E6CE 1  
FLOWSTBPERIOD Master-Strobe Half-Period D7  
[11]  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
00000010 RW  
00000000 RW  
GPIFTCB3  
GPIFTCB2  
GPIFTCB1  
GPIFTCB0  
reserved  
GPIF Transaction Count TC31  
Byte 3  
TC30  
TC29  
TC28  
TC27  
TC26  
TC25  
TC24  
[11]  
[11]  
[11]  
E6CF 1  
E6D0 1  
E6D1 1  
2
GPIF Transaction Count TC23  
Byte 2  
TC22  
TC14  
TC6  
TC21  
TC13  
TC5  
TC20  
TC12  
TC4  
TC19  
TC11  
TC3  
TC18  
TC10  
TC2  
TC17  
TC9  
TC1  
TC16  
TC8  
TC0  
00000000 RW  
00000000 RW  
00000001 RW  
00000000 RW  
GPIF Transaction Count TC15  
Byte 1  
GPIF Transaction Count TC7  
Byte 0  
Document #: 38-08032 Rev. *K  
Page 32 of 60  
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