CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
auto mode and it is desired to send two packets back to back:
a full packet (full defined as the number of bytes in the FIFO
meeting the level set in AUTOINLEN register) committed
automatically followed by a short one byte/word packet
committed manually using the PKTEND pin. In this particular
scenario, user must make sure to assert PKTEND at least one
clock cycle after the rising edge that caused the last byte/word
to be clocked into the previous auto committed packet.
Figure 10-12 below shows this scenario. X is the value the
AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
Figure 10-12 shows a scenario where two packets are being
committed. The first packet gets committed automatically
when the number of bytes in the FIFO reaches X (value set in
AUTOINLEN register) and the second one byte/word short
packet being committed manually using PKTEND. Note that
there is at least one IFCLK cycle timing between the assertion
of PKTEND and clocking of the last byte of the previous packet
(causing the packet to be committed automatically). Failing to
adhere to this timing, will result in the FX2 failing to send the
one byte/word short packet.
t
IFCLK
IFCLK
t
t
SFA
FAH
FIFOADR
>= t
WRH
>= t
SWR
SLWR
DATA
t
t
t
FDH
t
t
t
FDH
t
t
t
SFD
t
SFD
FDH
SFD
t
SFD
t
FDH
SFD
SFD
FDH
FDH
X-4
X-2
X-1
1
X-3
X
At least one IFCLK cycle
t
SPE
t
PEH
PKTEND
Figure 10-12. Slave FIFO Synchronous Write Sequence and Timing Diagram[20]
10.12 Slave FIFO Asynchronous Packet End Strobe
t
PEpwh
PKTEND
t
PEpwl
FLAGS
t
XFLG
Figure 10-13. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[20]
Table 10-14. Slave FIFO Asynchronous Packet End Strobe Parameters[23]
Parameter Description
Min.
50
Max.
Unit
ns
tPEpwl PKTEND Pulse Width LOW
tPWpwh
tXFLG
PKTEND Pulse Width HIGH
50
ns
PKTEND to FLAGS Output Propagation Delay
115
ns
Document #: 38-08032 Rev. *K
Page 47 of 60
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