CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
10.8
Slave FIFO Asynchronous Read
t
RDpwh
SLRD
t
RDpwl
t
XFLG
t
FLAGS
XFD
DATA
SLOE
N+1
N
t
t
OEoff
OEon
Figure 10-8. Slave FIFO Asynchronous Read Timing Diagram[20]
Table 10-8. Slave FIFO Asynchronous Read Parameters[23]
Parameter Description
tRDpwl SLRD Pulse Width LOW
Min.
50
Max.
Unit
ns
tRDpwh
tXFLG
tXFD
SLRD Pulse Width HIGH
50
ns
SLRD to FLAGS Output Propagation Delay
SLRD to FIFO Data Output Propagation Delay
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
70
15
ns
ns
tOEon
10.5
10.5
ns
tOEoff
ns
Note:
23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Document #: 38-08032 Rev. *K
Page 44 of 60
[+] Feedback
CYPRESS [ CYPRESS ]
