CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
EP2–1024 double buffered; EP6–512 quad buffered
(column 8).
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
EP0 IN&OUT
EP1 IN
EP1 OUT
EP2
EP2
512
EP2
EP2 EP2
EP2 EP2
EP2
512
EP2
EP2
512
EP2
EP2
512
512
512
512
512
512
512
1024
1024
1024
1024
512
512
512
512
512
1024
EP4
512
EP4 EP4
512
512
512
512
512
512
512
512
EP6
1024
1024
1024
1024
1024
512
512
512
512
EP6
512
EP6
512
EP6
EP6 EP6
EP6
EP6
EP6 EP6
512
512
1024
1024 1024
512
512
512
512
512
512
1024
1024
1024
512
512
512
512
EP8
512
EP8
512
EP8
512
EP8
512
EP8
512
1024
512
512
512
512
512
512
1024
1024
1024
512
512
512
512
512
10
11
12
9
4
5
8
1
2
3
6
7
Figure 3-5. Endpoint Configuration
3.12.5 Default Full-Speed Alternate Settings
Table 3-6. Default Full-Speed Alternate Settings[4, 5]
Alternate Setting
0
64
0
1
2
3
ep0
64
64
64
ep1out
ep1in
ep2
64 bulk
64 bulk
64 int
64 int
64 int
64 int
0
0
64 bulk out (2×)
64 bulk out (2×)
64 bulk in (2×)
64 bulk in (2×)
64 int out (2×)
64 bulk out (2×)
64 int in (2×)
64 iso out (2×)
64 bulk out (2×)
64 iso in (2×)
ep4
0
ep6
0
ep8
0
64 bulk in (2×)
64 bulk in (2×)
3.12.6 Default High-Speed Alternate Settings
Table 3-7. Default High-Speed Alternate Settings[4, 5]
Alternate Setting
0
1
2
3
ep0
64
0
64
64
64
ep1out
ep1in
ep2
512 bulk[6]
512 bulk[6]
64 int
64 int
0
64 int
64 int
0
512 bulk out (2×)
512 bulk out (2×)
512 bulk in (2×)
512 bulk in (2×)
512 int out (2×)
512 bulk out (2×)
512 int in (2×)
512 bulk in (2×)
512 iso out (2×)
512 bulk out (2×)
512 iso in (2×)
512 bulk in (2×)
ep4
0
ep6
0
ep8
0
Notes:
4. “0” means “not implemented.”
5. “2×” means “double buffered.”
6. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Document #: 38-08032 Rev. *K
Page 10 of 60
[+] Feedback
CYPRESS [ CYPRESS ]
