CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
There is no specific timing requirement that should be met for
asserting PKTEND pin to asserting SLWR. PKTEND can be
asserted with the last data value clocked into the FIFOs or
thereafter. The setup time t
SPE
and the hold time t
PEH
must be
met.
Although there are no specific timing requirements for the
PKTEND assertion, there is a specific corner case condition that
needs attention while using the PKTEND to commit a one byte
or word packet. There is an additional timing requirement that
needs to be met when the FIFO is configured to operate in auto
mode and it is required to send two packets back to back: a full
packet (full defined as the number of bytes in the FIFO meeting
the level set in AUTOINLEN register) committed automatically
followed by a short one byte or word packet committed manually
using the PKTEND pin. In this scenario, the user must ensure to
assert PKTEND at least one clock cycle after the rising edge that
caused the last byte or word to be clocked into the previous auto
committed packet.
shows this scenario. X is the
value the AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
shows a scenario where two packets are committed.
The first packet gets committed automatically when the number
of bytes in the FIFO reaches X (value set in AUTOINLEN
register) and the second one byte/word short packet being
committed manually using PKTEND.
Note that there is at least one IFCLK cycle timing between the
assertion of PKTEND and clocking of the last byte of the previous
packet (causing the packet to be committed automatically).
Failing to adhere to this timing results in the FX2 failing to send
the one byte or word short packet.
Figure 9-12. Slave FIFO Synchronous Write Sequence and Timing Diagram
t
IFCLK
IFCLK
t
SFA
t
FAH
FIFOADR
>= t
SWR
>= t
WRH
SLWR
t
SFD
t
FDH
t
SFD
X-3
t
FDH
t
SFD
X-2
t
FDH
t
SFD
X-1
t
FDH
t
SFD
X
t
FDH
t
SFD
1
t
FDH
DATA
X-4
At least one IFCLK cycle
t
SPE
t
PEH
PKTEND
9.12 Slave FIFO Asynchronous Packet End Strobe
Figure 9-13. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
t
PEpwh
PKTEND
t
PEpwl
FLAGS
t
XFLG
Table 27. Slave FIFO Asynchronous Packet End Strobe Parameters
Parameter
t
PEpwl
t
PWpwh
t
XFLG
Description
PKTEND pulse width LOW
PKTEND pulse width HIGH
PKTEND to FLAGS output propagation delay
Min
50
50
–
Max
–
–
115
Unit
ns
ns
ns
Document #: 38-08032 Rev. *V
Page 48 of 66
CYPRESS [ CYPRESS SEMICONDUCTOR ]
