CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 20. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
Parameter
t
IFCLK
t
SRD
t
RDH
t
OEon
t
OEoff
t
XFLG
t
XFD
IFCLK period
SLRD to clock setup time
Clock to SLRD hold time
SLOE turn on to FIFO data valid
SLOE turn off to FIFO data hold
Clock to FLAGS output propagation delay
Clock to FIFO data output propagation delay
Description
Min
20.83
12.7
3.7
–
–
–
–
Max
200
–
–
10.5
10.5
13.5
15
Unit
ns
ns
ns
ns
ns
ns
ns
9.8 Slave FIFO Asynchronous Read
Figure 9-8. Slave FIFO Asynchronous Read Timing Diagram
t
RDpwh
SLRD
t
RDpwl
t
XFLG
FLAGS
t
XFD
DATA
N
t
OEon
N+1
t
OEoff
SLOE
Table 21. Slave FIFO Asynchronous Read Parameters
Parameter
t
RDpwl
t
RDpwh
t
XFLG
t
XFD
t
OEon
t
OEoff
Description
SLRD pulse width LOW
SLRD pulse width HIGH
SLRD to FLAGS output propagation delay
SLRD to FIFO data output propagation delay
SLOE turn-on to FIFO data valid
SLOE turn-off to FIFO data hold
Min
50
50
–
–
–
–
Max
–
–
70
15
10.5
10.5
Unit
ns
ns
ns
ns
ns
ns
Note
23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Document #: 38-08032 Rev. *V
Page 45 of 66
CYPRESS [ CYPRESS SEMICONDUCTOR ]
