CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document History Page
Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB
®
FX2LP™ USB Microcontroller High-
Speed USB Peripheral Controller
Document Number: 38-08032
Orig. of
Rev. ECN No. Change Submission
Description of Change
Date
**
124316
VCS
03/17/03 New datasheet
*A 128461
VCS
09/02/03 Added PN CY7C68015A throughout datasheet
Modified
to add ECC block and fix errors
Removed word “compatible” where associated with I
2
C
Corrected grammar and formatting in various locations
Updated Sections 3.2.1, 3.9, 3.11,
Section 5.0
Added Sections 3.15, 3.18.4, 3.20
Modified
for clarity
Updated
to match current spec revision
*B 130335
KKV
10/09/03 Restored PRELIMINARY to header (had been removed in error from rev. *A)
*C 131673
KKU
02/12/04 Section 8.1 changed “certified” to “compliant”
added parameter V
IH_X
and V
IL_X
Added Sequence diagrams Section 9.16
Updated Ordering information with lead-free parts
Updated Registry Summary
Section 3.12.4:example changed to column 8 from column 9
Updated
memory write timing Diagram
Updated section 3.9 (reset)
Updated section 3.15 ECC Generation
*D 230713
KKU
See ECN Changed Lead free Marketing part numbers in
as per spec change in 28-00054.
*E 242398
TMD
See ECN Minor Change: datasheet posted to the web,
*F
271169
MON
See ECN Added USB-IF Test ID number
Added USB 2.0 logo
Added values for Isusp, Icc, Power Dissipation, Vih_x, Vil_x
Changed VCC from + 10% to + 5%
Changed PKTEND to FLAGS output propagation delay (asynchronous interface) in
from a max value of 70 ns to 115 ns
*G
316313 MON
See ECN Removed CY7C68013A-56PVXCT part availability
Added parts ideal for battery powered applications: CY7C68014A, CY7C68016A
Provided additional timing restrictions and requirement about the use of PKETEND pin to
commit a short one byte/word packet subsequent to committing a packet automatically
(when in auto mode).
Added Min Vcc Ramp Up time (0 to 3.3v)
*H
338901 MON
See ECN Added information about the AUTOPTR1/AUTOPTR2 address timing with regards to data
memory read/write timing diagram.
Removed TBD for Min value of Clock to FIFO Data Output Propagation Delay (t
XFD
) for
Slave FIFO Synchronous Read
Changed
to include part CY7C68016A-56LFXC in the part listed for battery
powered applications
Added register GPCR2 in register summary
*I
371097 MON
See ECN Added timing for strobing RD#/WR# signals when using PortC strobe feature (Section 9.5)
*J
397239
MON
See ECN Removed XTALINSRC register from register summary.
Changed Vcc margins to +10%
Added 56-pin VFBGA Pin Package Diagram
Added 56-pin VFBGA definition in pin listing
Added RDK part number to the Ordering Information table
*K 420505
MON
See ECN Remove SLCS from figure in Section 9.10.
Removed indications that SLRD can be asserted simultaneously with SLCS in Section
Added Absolute Maximum Temperature Rating for industrial packages in Section 5.
Changed number of packages stated in the description in Section 3. to five.
Added
on Thermal Coefficients for various packages
Document #: 38-08032 Rev. *V
Page 64 of 66
CYPRESS [ CYPRESS SEMICONDUCTOR ]
