FOR
FOR
CY7C68001
Table 6-1.
SX2
Pin Definitions
(continued)
QFN SSOP
Pin
Pin
1
2
29
30
31
13
8
9
36
37
38
20
Name
SLRD
SLWR
FLAGA
FLAGB
FLAGC
IFCLK
Type
Input
Input
Output
Output
Output
I/O/Z
Default
N/A
N/A
H
H
H
Z
Description
SLRD
is the input-only read strobe with programmable polarity (POLAR.3) for the
slave FIFOs connected to FD[7:0] or FD[15:0].
SLWR
is the input-only write strobe with programmable polarity (POLAR.2) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
FLAGA
is a programmable slave-FIFO output status flag signal.
Defaults to PF for the FIFO selected by the FIFOADR[2:0] pins.
FLAGB
is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[2:0] pins.
FLAGC
is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[2:0] pins.
Interface Clock,
used for synchronously clocking data into or out of the slave
FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals.
When using the internal clock reference (IFCONFIG.7=1) the IFCLK pin can be
configured to output 30/48 MHz by setting bits IFCONFIG.5 and IFCONFIG.6.
IFCLK may be inverted by setting the bit IFCONFIG.4=1. Programmable polarity.
Reserved.
Must be connected to ground.
USB Wakeup.
If the
SX2
is in suspend, asserting this pin starts up the oscillator
and interrupts the
SX2
to allow it to exit the suspend mode. During normal
operation, holding WAKEUP asserted inhibits the
SX2
chip from suspending. This
pin has programmable polarity (POLAR.7).
I
2
C Clock.
Connect to V
CC
with a 2.2K-10 K Ohms resistor, even if no I
2
C
EEPROM is attached.
I
2
C Data.
Connect to V
CC
with a 2.2K-10 K Ohms resistor, even if no I
2
C EEPROM
is attached.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
V
CC
. Connect to 3.3V power source.
Connect to ground.
Connect to ground.
Connect to ground.
Connect to ground.
Connect to ground.
Connect to ground.
Connect to ground.
14
44
21
51
Reserved
WAKEUP
Input
Input
N/A
N/A
15
16
22
23
SCL
SDA
OD
OD
Z
Z
55
7
11
17
27
32
43
53
56
10
12
26
28
41
6
14
18
24
34
39
50
4
7
17
19
33
35
48
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
GND
GND
GND
GND
GND
GND
GND
Power
Power
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Ground
Ground
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Document #: 38-08013 Rev. *E
Page 13 of 42
CYPRESS [ CYPRESS SEMICONDUCTOR ]
