FOR
FOR
CY7C68001
7.1
IFCONFIG
Bit #
Bit Name
IFCONFIG Register 0x01
0x01
7
IFCLKSRC
R/W
1
6
3048MHZ
R/W
1
5
IFCLKOE
R/W
0
4
IFCLKPOL
R/W
0
3
ASYNC
R/W
1
2
STANDBY
R/W
0
1
FLAGD/CS#
R/W
0
0
DISCON
R/W
1
Read/Write
Default
7.1.1
Bit 7: IFCLKSRC
This bit selects the clock source for the FIFOs. If IFCLKSRC
= 0, the external clock on the IFCLK pin is selected. If
IFCLKSRC = 1 (default), an internal 30 or 48 MHz clock is
used.
7.1.2
Bit 6: 3048MHZ
When ASYNC = 1 (default), the FIFOs operate asynchro-
nously. No clock signal input to IFCLK is required, and the
FIFO control signals function directly as read and write
strobes.
7.1.6
Bit 2: STANDBY
This bit selects the internal FIFO clock frequency. If 3048MHZ
= 0, the internal clock frequency is 30 MHz. If 3048MHZ = 1
(default), the internal clock frequency is 48 MHz.
7.1.3
Bit 5: IFCLKOE
This bit selects if the IFCLK pin is driven. If IFCLKOE = 0
(default), the IFCLK pin is floated. If IFCLKOE = 1, the IFCLK
pin is driven.
7.1.4
Bit 4: IFCLKPOL
This bit instructs the
SX2
to enter a low-power mode. When
STANDBY=1, the
SX2
will enter a low-power mode by turning
off its oscillator. The external master should write this bit after
it receives a bus activity interrupt (indicating that the host has
signaled a USB suspend condition). If
SX2
is disconnected
from the USB bus, the external master can write this bit at any
time to save power. Once suspended, the
SX2
is awakened
either by resumption of USB bus activity or by assertion of its
WAKEUP pin.
7.1.7
Bit 1: FLAGD/CS#
This bit controls the polarity of the IFCLK signal.
• When IFCLKPOL=0, the clock has the polarity shown in all
the timing diagrams in this data sheet (rising edge is the
activating edge).
• When IFCLKPOL=1, the clock is inverted (in some cases
may help with satisfying data set-up times).
7.1.5
Bit 3: ASYNC
This bit controls the function of the FLAGD/CS# pin. When
FLAGD/CS# = 0 (default), the pin operates as a slave chip
select. If FLAGD/CS# = 1, the pin operates as FLAGD.
7.1.8
Bit 0: DISCON
This bit controls whether the FIFO interface is synchronous or
asynchronous. When ASYNC = 0, the FIFOs operate synchro-
nously. In synchronous mode, a clock is supplied either inter-
nally or externally on the IFCLK pin, and the FIFO control
signals function as read and write enable signals for the clock
signal.
FLAGSAB
Bit #
Bit Name
Read/Write
Default
FLAGSCD
Bit #
Bit Name
Read/Write
Default
7
FLAGD3
R/W
0
6
FLAGD2
R/W
0
5
FLAGD1
R/W
0
4
7
FLAGB3
R/W
0
6
FLAGB2
R/W
0
5
FLAGB1
R/W
0
4
This bit controls whether the internal pull-up resistor
connected to D+ is pulled high or floating. When DISCON = 1
(default), the pull-up resistor is floating simulating a USB
unplug. When DISCON=0, the pull-up resistor is pulled high
signaling a USB connection.
7.2
FLAGSAB/FLAGSCD Registers 0x02/0x03
The
SX2
has four FIFO flags output pins: FLAGA, FLAGB,
FLAGC, FLAGD.
0x02
3
FLAGA3
R/W
0
2
FLAGA2
R/W
0
1
FLAGA1
R/W
0
0
FLAGA0
R/W
0
0x03
3
FLAGC3
R/W
0
2
FLAGC2
R/W
0
1
FLAGC1
R/W
0
0
FLAGC0
R/W
0
FLAGB0
R/W
0
FLAGD0
R/W
0
Document #: 38-08013 Rev. *E
Page 15 of 42
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