CY7C64013
CY7C64113
tCYC
tCH
CLOCK
tCL
Figure 23-1. Clock Timing
tr
tr
D+
D−
90%
90%
10%
10%
Figure 23-2. USB Data Signal Timing
Interrupt Generated
Int
CS (P2.6, input)
OE (P2.5, input)
DATA (output)
tRD
D[23:0]
tOED
tOEZ
STB (P2.4, input)
tOEDR
(Ready)
DReadyPin (P2.3, output)
(Shown for DRDY Polarity=0)
Internal Write
Internal Addr
Port0
Figure 23-3. HAPI Read by External Interface from USB Microcontroller
Document #: 38-08001 Rev. **
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