FOR
FOR
CY7C63411/12/13
CY7C63511/12/13
CY7C63612/13
TABLE OF CONTENTS
1.0 FEATURES ..................................................................................................................................... 5
2.0 FUNCTIONAL OVERVIEW ............................................................................................................. 6
3.0 PIN ASSIGNMENTS ....................................................................................................................... 8
4.0 PROGRAMMING MODEL ............................................................................................................... 8
4.1
4.2
4.3
4.4
4.5
4.6
14-bit Program Counter (PC) ........................................................................................................... 8
8-bit Accumulator (A) ....................................................................................................................... 8
8-bit Index Register (X) .................................................................................................................... 8
8-bit Program Stack Pointer (PSP) .................................................................................................. 9
8-bit Data Stack Pointer (DSP) ........................................................................................................ 9
Address Modes ................................................................................................................................ 9
4.6.1 Data ........................................................................................................................................................ 9
4.6.2 Direct ...................................................................................................................................................... 9
4.6.3 Indexed ................................................................................................................................................... 9
5.0 INSTRUCTION SET SUMMARY ................................................................................................... 11
6.0 MEMORY ORGANIZATION .......................................................................................................... 12
6.1 Program Memory Organization ...................................................................................................... 12
6.2 Data Memory Organization ............................................................................................................ 13
6.3 I/O Register Summary ................................................................................................................... 14
7.0 CLOCKING .................................................................................................................................... 15
8.0 RESET ........................................................................................................................................... 15
8.1 Power-On Reset (POR) ................................................................................................................. 15
8.2 Watch Dog Reset (WDR) ............................................................................................................... 16
9.0 GENERAL PURPOSE I/O PORTS ............................................................................................... 16
9.1 GPIO Interrupt Enable Ports .......................................................................................................... 17
9.2 GPIO Configuration Port ................................................................................................................ 18
10.0 DAC PORT .................................................................................................................................. 19
10.1 DAC Port Interrupts ..................................................................................................................... 19
10.2 DAC Isink Registers ..................................................................................................................... 20
11.0 USB SERIAL INTERFACE ENGINE (SIE) ................................................................................. 20
11.1 USB Enumeration ........................................................................................................................ 20
11.2 PS/2 Operation ............................................................................................................................ 20
11.3 USB Port Status and Control ....................................................................................................... 21
12.0 USB DEVICE ............................................................................................................................... 21
12.1 USB Ports .................................................................................................................................... 21
12.2 Device Endpoints (3) ................................................................................................................... 21
13.0 12-BIT FREE-RUNNING TIMER ................................................................................................. 22
13.1 Timer (LSB) ................................................................................................................................. 22
13.2 Timer (MSB) ................................................................................................................................ 22
14.0 PROCESSOR STATUS AND CONTROL REGISTER ............................................................... 23
15.0 INTERRUPTS .............................................................................................................................. 24
15.1 Interrupt Vectors .......................................................................................................................... 24
Document #: 38-08027 Rev. **
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CYPRESS [ CYPRESS SEMICONDUCTOR ]
