CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage ..........................................> 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.....................................................>200mA
Storage Temperature ...................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Ambient
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Range
Commercial
Industrial[4]
Temperature
VCC
DC Voltage Applied to Outputs
in High-Z State............................................... –0.5V to +7.0V
0°C to +70°C
5V ±10%
5V ±10%
–40°C to +85°C
DC Input Voltage............................................ –3.0V to +7.0V
Pin Definitions
Pin
Name
I/O
Description
D0–8
Q0–8
Data Inputs
I
O
I
Data Inputs for 9-bit Bus
Data Outputs for 9-bit Bus
Data Outputs
Write Enable 1
WEN1
The only Write enable to have programmable flags when device is configured. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two Write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD Dual Write Enable 2
I
I
If HIGH at reset, this pin operates as a second Write enable. If LOW at reset, this pin
operates as a control to Write or Read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
Mode Pin
Load
REN1, REN2 Read Enable
Inputs
I
I
Enables Device for Read Operation
WCLK
Write Clock
The rising edge clocks data into the FIFO when WEN1is LOW, WEN2/LD is HIGH, and the
FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1and REN2 are LOW and the FIFO
is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset
register.
EF
Empty Flag
Full Flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Programmable
Almost Empty
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-
grammed into the FIFO.
PAF
RS
Programmable
Almost Full
O
I
When PAFis LOW, the FIFO is almost full based on the almost full offset value programmed into
the FIFO.
Reset
Resets device to empty condition. A reset is required before an initial Read or Write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is
HIGH, the FIFO’s outputs are in High-Z (high-impedance) state.
Note:
4. TA is the “instant on” case temperature.
Document #: 38-06016 Rev. *A
Page 6 of 18
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