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CY7C4251-15AC 参数 Datasheet PDF下载

CY7C4251-15AC图片预览
型号: CY7C4251-15AC
PDF下载: 下载PDF文件 查看货源
内容描述: 的64/256 / 512 / 1K / 2K / 4K / 8K ×9同步FIFO的 [64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs]
分类和应用: 先进先出芯片
文件页数/大小: 18 页 / 412 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号CY7C4251-15AC的Datasheet PDF文件第1页浏览型号CY7C4251-15AC的Datasheet PDF文件第2页浏览型号CY7C4251-15AC的Datasheet PDF文件第4页浏览型号CY7C4251-15AC的Datasheet PDF文件第5页浏览型号CY7C4251-15AC的Datasheet PDF文件第6页浏览型号CY7C4251-15AC的Datasheet PDF文件第7页浏览型号CY7C4251-15AC的Datasheet PDF文件第8页浏览型号CY7C4251-15AC的Datasheet PDF文件第9页  
CY7C4421/4201/4211/4221  
CY7C4231/4241/4251  
When the device is configured for programmable flags and  
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH  
transition of WCLK writes data from the data inputs to the  
empty offset least significant bit (LSB) register. The second,  
third, and fourth LOW-to-HIGH transitions of WCLK store data  
in the empty offset most significant bit (MSB) register, full offset  
LSB register, and full offset MSB register, respectively, when  
WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH  
transition of WCLK while WEN2/LD and WEN1 are LOW  
writes data to the empty LSB register again. Figure 1 shows  
the registers sizes and default values for the various device  
types.  
It is not necessary to write to all the offset registers at one time.  
A subset of the offset registers can be written; then by bringing  
the WEN2/LD input HIGH, the FIFO is returned to normal  
Read and Write operation. The next time WEN2/LD is brought  
LOW, a Write operation stores data in the next offset register  
in sequence.  
The contents of the offset registers can be read to the data  
outputs when WEN2/LD is LOW and both REN1 and REN2  
are LOW. LOW-to-HIGH transitions of RCLK Read register  
contents to the data outputs. Writes and reads should not be  
preformed simultaneously on the offset registers.  
64 ×9  
256 ×9  
512 ×9  
1K ×9  
0
0
0
0
0
0
0
0
0
0
0
0
0
8
8
8
8
6 5  
8
8
8
8
7
8
8
8
8
7
8
8
8
8
7
Empty Offset (LSB) Reg.  
Default Value= 007h  
Empty Offset (LSB) Reg.  
Default Value = 007h  
Empty Offset (LSB) Reg.  
Default Value = 007h  
Empty Offset (LSB) Reg.  
Default Value = 007h  
0
0
0
1
1
(MSB)  
0
(MSB)  
00  
6 5  
7
7
7
Full Offset (LSB) Reg  
Default Value= 007h  
Full Offset (LSB) Reg  
Default Value = 007h  
Full Offset (LSB) Reg  
Default Value = 007h  
Full Offset (LSB) Reg  
Default Value = 007h  
1
1
(MSB)  
0
(MSB)  
00  
2K ×9  
4K ×9  
8K ×9  
0
0
0
0
0
0
0
0
0
8
8
8
8
7
8
8
8
8
7
8
8
8
8
7
Empty Offset (LSB) Reg.  
Default Value= 007h  
Empty Offset (LSB) Reg.  
Default Value = 007h  
Empty Offset (LSB) Reg.  
Default Value = 007h  
0
0
0
2
3
4
(MSB)  
0000  
(MSB)  
00000  
(MSB)  
000  
7
7
7
Full Offset (LSB) Reg  
Default Value= 007h  
Full Offset (LSB) Reg  
Default Value = 007h  
Full Offset (LSB) Reg  
Default Value = 007h  
2
3
4
(MSB)  
000  
(MSB)  
0000  
(MSB)  
00000  
Figure 1. Offset Register Location and Default Values  
Document #: 38-06016 Rev. *A  
Page 3 of 18  
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