CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Read Cycle Timing
t
CKL
t
t
CLKL
CLKH
RCLK
t
t
ENH
ENS
REN1,REN2
NO OPERATION
t
REF
t
REF
EF
t
A
VALID DATA
Q
–Q
8
0
t
OLZ
t
OHZ
t
OE
OE
[15]
t
SKEW1
WCLK
WEN1
WEN2
Reset Timing[16]
t
RS
RS
t
t
t
RSR
RSS
RSS
REN1,
REN2
t
RSR
WEN1
t
t
RSR
RSS
[17]
WEN2/LD
t
t
t
RSF
RSF
RSF
EF,PAE
FF,PAF,
[18]
E
O =1
Q
Q
8
0 -
OE=0
Notes:
14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
15. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK rising edge.
Document #: 38-06016 Rev. *A
Page 9 of 18
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