CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Characteristics
Over the Operating Range (Speeds -35, -45, -55)
7C132-35
7C136-35
7C142-35
7C146-35
Min
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD
t
DDD
t
WDD
Cycle
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
R/W Pulse Width
Data Setup to Write End
Data Hold from Write End
R/W LOW to High Z
R/W HIGH to Low Z
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
5
0
30
35
Note 15
Note 15
0
20
20
20
20
5
0
35
45
Note 15
Note 15
35
30
30
2
0
25
15
0
20
0
25
25
25
25
5
0
35
45
Note 15
Note 15
45
35
35
2
0
30
20
0
20
0
30
30
30
30
55
40
40
2
0
30
20
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power
Parameter
Description
7C132-45
7C136-45
7C142-45
7C146-45
Min
45
Max
7C132-55
7C136-55
7C136A-55
7C142-55
7C146-55
Min
55
Max
Unit
Max
35
35
0
35
20
3
20
5
20
0
35
ns
55
ns
ns
55
25
ns
ns
ns
25
ns
ns
25
ns
ns
35
ns
45
0
45
25
3
20
5
20
0
35
0
5
3
0
Down
Busy/Interrupt Timing
Document #: 38-06031 Rev. *E
Page 6 of 15
CYPRESS [ CYPRESS SEMICONDUCTOR ]
