CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Waveforms
(continued)
Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
t
WC
ADDRESS
t
SCE
CE
t
SA
R/W
t
SD
DATA
IN
t
HZWE
D
OUT
t
HD
t
AW
t
PWE
t
HA
DATA VALID
t
LZWE
HIGH IMPEDANCE
Figure 9. Busy Timing Diagram No. 1 (CE Arbitration)
CE
L
Valid First:
ADDRESS
L,R
CE
L
t
PS
CE
R
t
BLC
BUSY
R
t
BHC
ADDRESS MATCH
CE
R
Valid First:
ADDRESS
L,R
CE
R
t
PS
CE
L
t
BLC
BUSY
L
t
BHC
ADDRESS MATCH
Note
21. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state.
Document #: 38-06031 Rev. *E
Page 9 of 15
CYPRESS [ CYPRESS SEMICONDUCTOR ]
