CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Characteristics
Over the Operating Range (Speeds -15, -25, -30)
[8]
(continued)
7C136-15
7C146-15
Min
Write
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD
t
DDD
t
WDD
t
WINS
t
EINS
t
INS
t
OINR
t
EINR
t
INR
Cycle
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
R/W Pulse Width
Data Setup to Write End
Data Hold from Write End
R/W LOW to High Z
R/W HIGH to Low Z
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset
Time
[4]
Parameter
Description
7C132-25
[4]
7C136-25
7C142-25
7C146-25
Min
25
20
20
2
0
15
15
0
Max
7C132-30
7C136-30
7C142-30
7C146-30
Min
30
25
25
2
0
25
15
0
Max
Unit
Max
15
12
12
2
0
12
10
0
10
0
15
15
15
15
5
0
13
15
Note 15
Note 15
15
15
15
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
15
ns
ns
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
30
Note 15
Note 15
25
25
25
25
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
0
20
20
20
20
5
0
20
25
Note 15
Note 15
25
25
25
25
25
25
5
0
30
0
Busy/Interrupt Timing
Interrupt Timing
CE to INTERRUPT Reset Time
Address to INTERRUPT Reset
Time
Shaded areas contain preliminary information.
Notes
12. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
13. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.
14. CY7C142/CY7C146 only.
15. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
16. 52-pin PLCC and PQFP versions only.
Document #: 38-06031 Rev. *E
Page 5 of 15
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