CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Waveforms
(continued)
Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A)
t
RC
ADDRESS
R
R/W
R
D
INR
t
PS
ADDRESS
L
BUSY
L
t
BLA
DOUT
L
t
WDD
t
DDD
ADDRESS MATCH
t
BHA
t
BDD
VALID
ADDRESS MATCH
t
PWE
VALID
Figure 7. Write Cycle No.1 (OE Three-States Data I/Os—Either Port)
t
WC
ADDRESS
t
SCE
CE
t
SA
R/W
t
SD
DATA
IN
DATA VALID
t
HD
t
AW
t
HA
t
PWE
OE
t
HZOE
HIGH IMPEDANCE
D
OUT
Note
20. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or t
HZWE
+ t
SD
to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required t
SD
.
Document #: 38-06031 Rev. *E
Page 8 of 15
CYPRESS [ CYPRESS SEMICONDUCTOR ]
