CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Pin Definitions
Name
A
0
, A
1
, A
IO
Description
Input-
Address inputs used to select one of the address locations.
Sampled at the rising edge of
Synchronous the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3 [2]
are sampled active. A1: A0
are fed to the two-bit counter..
Input-
Byte write select inputs, active LOW.
Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
Input-
Global write enable input, active LOW.
When asserted LOW on the rising edge of CLK, a
Synchronous global write is conducted (all bytes are written, regardless of the values on BW
X
and BWE).
Input-
Byte write enable input, active LOW.
Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-
Clock
Clock input.
Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
BW
A
, BW
B
BW
C
, BW
D
GW
BWE
CLK
CE
1
Input-
Chip enable 1 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE and CE to select or deselect the device. ADSP is ignored if CE is HIGH. CE is sampled
2
3
1
1
only when a new external address is loaded.
Input-
Chip enable 2 input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction
Synchronous with CE
1
and CE
3
to select or deselect the device. CE
2
is sampled only when a new external
address is loaded.
Input-
Chip enable 3 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE
1
and CE
2
to select or deselect the device. CE
3
is sampled only when a new external address
is loaded.
Input-
Output enable, asynchronous input, active LOW.
Controls the direction of the IO pins. When
Asynchronous LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Input-
Advance input signal, sampled on the rising edge of CLK, active LOW.
When asserted, it
Synchronous automatically increments the address in a burst cycle.
Input-
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE
1
is deasserted HIGH.
Input-
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
Input-
ZZ sleep input.
This active HIGH input places the device in a non-time critical sleep condition
Asynchronous with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
IO-
Bidirectional data IO lines.
As inputs, they feed into an on-chip data register that is triggered
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP
X
are placed in a tri-state condition.
Power Supply
Power supply inputs to the core of the device.
CE
2 [2]
CE
3 [2]
OE
ADV
ADSP
ADSC
ZZ
DQs, DQP
X
V
DD
Document #: 38-05543 Rev. *E
Page 6 of 30
CYPRESS [ CYPRESS SEMICONDUCTOR ]
