CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it will directly control the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it will enable the output buffers to
drive the output bus. When LOW, this bit will place the output
bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is powered
up, and also when the TAP controller is in the Test-Logic-Reset
state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
Test Clock
(TCK)
t TMSS
t TH
t TMSH
t
TL
t CYC
Test Mode Select
(TMS)
t TDIS
t TDIH
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
Parameter
Clock
t
TCYC
t
TF
t
TH
t
TL
t
TDOV
t
TDOX
Setup Times
t
TMSS
t
TDIS
t
CS
Hold Times
t
TMSH
t
TDIH
t
CH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
0
20
20
10
50
20
ns
MHz
ns
ns
ns
ns
Description
Min.
Max.
Unit
Output Times
Notes:
10. t
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1ns.
Document #: 38-05543 Rev. *E
Page 13 of 30
CYPRESS [ CYPRESS SEMICONDUCTOR ]
