CY7C185
Switching Waveforms
Read Cycle No.1
[8,9]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Read Cycle No.2
[10,11]
CE
1
t
RC
CE
2
OE
OE
t
ACE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
ICC
50%
ISB
HIGH
IMPEDANCE
DATA OUT
Notes:
8. Device is continuously selected. OE, CE
1
= V
IL
. CE
2
= V
IH
.
9. WE is HIGH for read cycle.
10. Data I/O is High Z if OE = V
IH
, CE
1
= V
IH
, WE = V
IL
, or CE
2
=V
IL
.
11. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH and WE LOW. CE
1
and WE must be LOW and CE
2
must be HIGH
to initiate write. A write can be terminated by CE
1
or WE going HIGH or CE
2
going LOW. The data input set-up and hold timing should be referenced to the
rising edge of the signal that terminates the write.
Document #: 38-05043 Rev. *B
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