CY7C1360B
CY7C1362B
Truth Table[3, 4, 5, 6, 7, 8]
Operation
Add. Used
None
CE2
X
L
X
L
CE3
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
WRITE
CLK
DQ
CE1
H
L
L
L
L
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
ZZ ADSP ADSC ADV
OE
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Snooze Mode, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
H
H
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
L-H Three-State
None
None
None
None
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
L-H
Three-State
Q
External
External
External
External
External
Next
Next
Next
Next
Next
L
L-H Three-State
L-H
L-H
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
D
Q
L-H Three-State
L-H
L-H Three-State
L-H
L-H Three-State
L-H
L-H
L-H
L-H Three-State
L-H
L-H Three-State
L-H
L-H
Q
L
L
L
L
Q
D
D
Q
Next
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
Q
D
D
WRITE Cycle, Suspend Burst
L
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
6. CE , CE , and CE are available only in the TQFP package. BGA package has only 2 chip selects CE and CE .
1
2
3
1
2
X
after the
or with the assertion of
. As a result,
must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state.
is
OE
ADSC
OE
ADSP
a don't care for the remainder of the Write cycle
8.
is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE
OE
is
.
is active (LOW)
inactive or when the device is deselected, and all data bits behave as output when
OE
9. Table only lists a partial listing of the byte write combinations. Any combination of BW
is valid. Appropriate write will be done based on which byte write is active.
[A:D]
Document #: 38-05291 Rev. *C
Page 14 of 34
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