CY7C1338
Pin Descriptions
Pin Number
85
Name
ADSC
I/O
Input-
Synchronous
Input-
Synchronous
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
LOW, A
[16:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
LOW, A
[16:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE
1
is deasserted HIGH.
A
1
, A
0
Address Inputs. These inputs feed the on-chip burst counter as the LSBs as
well as being used to access a particular memory location in the memory array.
Address Inputs used in conjunction with A
[1:0]
to select one of the 64K address loca-
tions. Sampled at the rising edge of the CLK, if CE
1
, CE
2
, and CE
3
are sampled active,
and ADSP or ADSC is active LOW.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
Sampled on the rising edge. BW
0
controls DQ
[7:0]
and DP
0
, BW
1
controls DQ
[15:8]
and
DP
1
, BW
2
controls DQ
[23:16]
and DP
2
, and BW
3
controls DQ
[31:24]
and DP
3
. See Write
Cycle Descriptions table for further details.
Advance Input used to advance the on-chip address counter. When LOW the internal
burst counter is advanced in a burst sequence. The burst sequence is selected using
the MODE input.
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is
used to conduct a global write, independent of the state of BWE and BW
[3:0]
. Global
writes override byte writes.
Clock Input. Used to capture all synchronous inputs to the device.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE
2
and CE
3
to select/deselect the device. CE
1
gates ADSP.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in con-
junction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE
1
and CE
2
to select/deselect the device.
84
ADSP
36, 37
49−44,
81–82,
99–100,
32–35
96–93
A
[1:0]
A
[16:2]
Input-
Synchronous
Input-
Synchronous
BW
[3:0]
Input-
Synchronous
83
ADV
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
87
88
BWE
GW
89
98
97
92
86
CLK
CE
1
CE
2
CE
3
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins.
Input-
Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power
Asynchronous standby mode in which all other inputs are ignored, but the data in the memory array
is maintained. Leaving ZZ floating or NC will default the device into an active state.
ZZ pin has an internal pull-down.
-
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. When left floating or NC, de-
faults to interleaved burst order. Mode pin has an internal pull-up.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[16:0]
during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE in conjunction with the internal control
logic. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
[31:0]
and DP
[3:0]
are placed in a three-state condition. The outputs are automatically
three-stated when a WRITE cycle is detected.
64
ZZ
31
MODE
29–28,
25–22,
19–18,
13–12, 9–6,
3–2, 79–78,
75–72,
69–68,
63–62,
59–56,
53–52
15, 41, 65,
91
DQ
[31:0]
I/O-
Synchronous
V
DD
Power Supply
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
3
CYPRESS [ CYPRESS SEMICONDUCTOR ]
