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CY7C1338-100AC 参数 Datasheet PDF下载

CY7C1338-100AC图片预览
型号: CY7C1338-100AC
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×32的同步,流通型3.3V高速缓存RAM [128K x 32 Synchronous-Flow-Through 3.3V Cache RAM]
分类和应用:
文件页数/大小: 16 页 / 277 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C1338
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IH
V
IL
V
IL
I
X
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Input LOW Voltage
[5]
Input LOW Voltage
[5]
Input Load Current
(except ZZ and MODE)
Input Current of MODE
Input Current of ZZ
I
OZ
I
OS
I
DD
Output Leakage Current
Output Short Circuit Current
[7]
V
DD
Operating Supply Current
Test Conditions
V
DDQ
= 3.3V, V
DD
= Min., I
OH
= –4.0 mA
V
DDQ
= 2.5V, V
DD
= Min., I
OH
= –2.0 mA
V
DDQ
= 3.3V, V
DD
= Min., I
OL
= 8.0 mA
V
DDQ
= 2.5V, V
DD
= Min., I
OL
= 2.0 mA
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
GND
V
I
V
DDQ
Input = V
SS
Input = V
DDQ
Input = V
SS
Input = V
DDQ
GND
V
I
V
DD,
Output Disabled
V
DD
= Max., V
OUT
= GND
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
I
SB1
Automatic CE Power-Down
Current—TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
,
f = f
MAX
= 1/t
CYC
,
inputs switching
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
I
SB2
Automatic CE Power-Down
Current — CMOS Inputs
Automatic CE Power-Down
Current—CMOS Inputs
Max. V
DD
, Device Deselected, All speeds
V
IN
0.3V or V
IN
> V
DDQ
– 0.3V,
f = 0, inputs static
Max. V
DD
, Device Deselected,
8.5-ns cycle, 117 MHz
V
IN
V
DDQ
– 0.3V or V
IN
0.3V,
10-ns cycle, 100 MHz
f = f
MAX
, inputs switching
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
I
SB4
Automatic CE Power-Down Current Max. V
DD
, Device Deselected,
— CMOS Inputs
V
IN
V
DD
– 0.3V or V
IN
0.3V,
f = 0, inputs static
All speeds
–5
–5
30
5
–300
350
325
300
250
125
110
100
90
10
2.0
1.7
–0.3
–0.3
−1
–30
5
Min.
2.4
2.0
0.4
0.7
V
DD
+
0.3V
V
DD
+
0.3V
0.8
0.7
1
Max.
Unit
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
I
SB3
95
85
75
65
30
mA
mA
mA
mA
mA
Note:
7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
8