CY7C1338
Capacitance
[8]
Parameter
C
IN
C
I/O
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
DD
= 5.0V
Max.
4
4
Unit
pF
pF
AC Test Loads and Waveforms
R1=317Ω
OUTPUT
Z
0
=50Ω
R
L
=50
Ω
5 pF
V
L
=1.5V
INCLUDING
JIG AND
SCOPE
R2=351Ω
GND
≤
3.0 ns
3.3V
OUTPUT
ALL INPUT PULSES
3.0V
10%
90%
90%
10%
≤
3.0 ns
(a)
(b)
Switching Characteristics
Over the Operating Range
[9]
-117
Parameter
t
CYC
t
CH
t
CL
t
AS
t
AH
t
CDV
t
DOH
t
ADS
t
ADH
t
WES
t
WEH
t
ADVS
t
ADVH
t
DS
t
DH
t
CES
t
CEH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
t
EOV
Clock HIGH
Clock LOW
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWS
[1:0]
, GW, BWE Set-Up Before CLK Rise
BWS
[1:0]
, GW, BWE Hold After CLK Rise
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Enable Set-Up
Chip Enable Hold After CLK Rise
Clock to High-Z
[10, 11]
-100
Min.
10
4.0
4.0
2.0
0.5
Max.
11
4.5
4.5
2.0
0.5
8.0
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
3.5
0
0
3.5
0
0
3.5
-90
Min.
Max.
20
4.5
4.5
2.0
0.5
8.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
3.5
0
3.5
0
3.5
-50
Min.
Max. Unit
ns
ns
ns
ns
ns
11.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.5
3.5
3.5
ns
ns
ns
ns
ns
Description
Clock Cycle Time
Min.
8.5
3.0
3.0
2.0
0.5
Max.
7.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
3.5
0
3.5
0
3.5
Clock to Low-Z
[10, 11]
OE HIGH to Output High-Z
[10, 12]
OE LOW to Output Low-Z
[10, 12]
OE LOW to Output Valid
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
9. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified I
OL
/I
OH
and load capacitance. Shown in (a) and (b) of AC test loads.
10. t
CHZ
, t
CLZ
, t
EOHZ
, and t
EOLZ
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
200 mV from steady-state voltage.
11. At any given voltage and temperature, t
CHZ
(max) is less than t
CLZ
(min).
12. This parameter is sampled and not 100% tested.
9
CYPRESS [ CYPRESS SEMICONDUCTOR ]
