CY7C1329
Capacitance
[9]
Parameter
C
IN
C
CLK
C
I/O
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
DD
= 3.3V,
V
DDQ
= 3.3V
Max.
4
4
4
Unit
pF
pF
pF
AC Test Loads and Waveforms
OUTPUT
Z
0
= 50Ω
R
L
= 50Ω
V
L
= 1.5V
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R = 317Ω
ALL INPUT PULSES
3.3V
R = 351Ω
GND
10%
90%
[10]
90%
10%
< 3.3 ns
< 3.3 ns
(a)
(b)
(c)
Switching Characteristics
Over the Operating Range
[11,12,13]
-133
Parameter
t
CYC
t
CH
t
CL
t
AS
t
AH
t
CO
t
DOH
t
ADS
t
ADH
t
WES
t
WEH
t
ADVS
t
ADVH
t
DS
t
DH
t
CES
t
CEH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
t
EOV
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWE, GW, BW[3:0] Set-up Before CLK Rise
BWE, GW, BW[3:0] Hold After CLK Rise
ADV Set-up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-up Before CLK Rise
Data Input Hold After CLK Rise
Chip Select Set-up
Chip Select Hold After CLK Rise
Clock to High-Z
[12]
Clock to Low-Z
[12]
-100
Max.
Min.
10
3.2
3.2
2.5
0.5
4.2
5.0
2.0
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
3.5
3.5
1.5
0
5.5
0
4.2
5.0
5
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
7.5
1.9
1.9
1.5
0.5
1.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0
OE HIGH to Output
High-Z
[12, 13]
[12, 13]
OE LOW to Output Low-Z
0
OE LOW to Output Valid
[12]
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10. Input waveform should have a slew rate of 1V/ns.
11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified I
OL
/I
OH
and load capacitance. Shown in (a) and (b) of AC Test Loads.
12. t
CHZ
, t
CLZ
, t
EOV
, t
EOLZ
, and t
EOHZ
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
200 mV from steady-state
voltage.
13. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
.
Document #: 38-05279 Rev. *B
Page 8 of 15
CYPRESS [ CYPRESS SEMICONDUCTOR ]
