CY7C1329
Switching Waveforms
(continued)
Read/Write Cycle Timing
[14,15,16, 17]
Single Read
t
CYC
Single Write
t
CH
Burst Read
Pipelined Read
Unselected
CLK
t
ADS
t
ADH
t
CL
ADSP ignored with CE
1
inactive
ADSP
t
ADS
ADSC
t
ADVS
t
ADH
ADV
t
AS
t
ADVH
RD1
t
AH
WD2
RD3
ADD
GW
t
WS
t
WH
t
WS
WE
t
CES
t
CEH
t
WH
CE
1
masks ADSP
CE
1
CE
2
t
CES
t
CEH
CE
3
t
CES
t
CEH
t
DOE
t
OEHZ
t
OELZ
t
CO
See Note 17
OE
t
DS
3a
Out
t
DH
3b
Out
3c
Out
t
DOH
3d
Out
T
CHZ
Data-
In/Out
1a
1a
Out
2a
In
= DON’T CARE
2a
Out
= UNDEFINED
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
Document #: 38-05279 Rev. *B
Page 11 of 15