CY7C131-55JC 参数 Datasheet PDF下载

CY7C130/CY7C131

CY7C140/CY7C141

Switching Waveforms

(continued)

Write Cycle No. 2 (R/W Three-States Data I/Os - Either Port)

Either Port

t

WC

ADDRESS

t

SCE

CE

t

SA

R/W

t

SD

DATA

IN

t

HZWE

DATA

OUT

C130-11

[16, 23]

t

HA

t

AW

t

PWE

t

HD

DATA VALID

t

LZWE

HIGH IMPEDANCE

Busy Timing Diagram No. 1 (CE Arbitration)

CE

L

Valid First:

ADDRESS

L,

R

CE

L

t

PS

CE

R

t

BLC

BUSY

R

t

BHC

ADDRESS MATCH

C130-12

CE

R

Valid First:

ADDRESS

L,R

CE

R

t

PS

CE

L

ADDRESS MATCH

t

BLC

BUSY

L

t

BHC

C130-13

Note:

23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state

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