CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms
(continued)
Read Cycle No. 2
[19, 21]
CE
OE
t
ACE
t
DOE
t
HZOE
t
HZCE
Either Port CE/OE Access
t
LZOE
t
LZCE
DATA OUT
t
PU
I
CC
I
SB
DATA VALID
t
PD
C130-8
Read Cycle No.3
[20]
Read with BUSY, Master: CY7C130 and CY7C131
t
RC
ADDRESS
R
R/W
R
D
INR
ADDRESS MATCH
t
PWE
t
HD
VALID
ADDRESS
L
t
PS
BUSY
L
t
BLA
DOUT
L
ADDRESS MATCH
t
BHA
t
BDD
VALID
t
WDD
t
DDD
C130-9
Write Cycle No.1 (OE Three-States Data I/Os - Either Port)
Either Port
t
WC
ADDRESS
t
SCE
CE
t
SA
R/W
t
AW
[15, 22]
t
PWE
t
HA
t
SD
DATA
IN
DATA VALID
t
HD
OE
t
HZOE
HIGH IMPEDANCE
D
OUT
C130-10
Notes:
21. Address valid prior to or coincident with CE transition LOW.
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or t
HZWE
+ t
SD
to allow the data I/O pins to enter high impedance and for data
to be placed on the bus for the required t
SD
.
7
CYPRESS [ CYPRESS SEMICONDUCTOR ]
