CY7C130/CY7C131
CY7C140/CY7C141
Switching Characteristics
Over the Operating Range
[6,11]
(continued)
7C130-35
7C131-35
7C140-35
7C141-35
Parameter
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB[17]
t
WH
t
BDD
t
DDD
t
WDD
[15]
7C130-45
7C131-45
7C140-45
7C141-45
Min.
45
35
35
2
0
30
20
0
Max.
7C130-55
7C131-55
7C140-55
7C141-55
Min.
55
40
40
2
0
30
20
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
25
0
ns
ns
30
30
30
30
5
0
35
ns
ns
ns
ns
ns
ns
ns
45
Note
18
Note
18
45
45
45
45
45
45
ns
ns
ns
Description
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
Data Set-Up to Write End
Data Hold from Write End
R/W LOW to High Z
[14]
R/W HIGH to Low Z
[14]
BUSY LOW from Address Match
BUSY HIGH from Address
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
[16]
Port Set Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
Mismatch
[16]
Min.
35
30
30
2
0
25
15
0
Max.
20
0
20
20
20
20
5
0
30
35
Note
18
Note
18
25
25
25
25
25
25
5
0
35
0
20
BUSY/INTERRUPT TIMING
25
25
25
25
45
Note
18
Note
18
35
35
35
35
35
35
INTERRUPT TIMING
t
WINS
t
EINS
t
INS
t
OINR
t
EINR
t
INR
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time
[16]
CE to INTERRUPT Reset
Address to
Time
[16]
INTERRUPT Reset Time
[16]
ns
ns
ns
ns
ns
ns
Switching Waveforms
[19, 20]
Read Cycle No.1
Either Port Address Access
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATAVALID
t
AA
DATA VALID
C130-7
Notes:
19. R/W is HIGH for read cycle.
20. Device is continuously selected, CE = V
IL
and OE = V
IL
.
6
CYPRESS [ CYPRESS SEMICONDUCTOR ]
