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CY7C1019DV33-10ZSXI 参数 Datasheet PDF下载

CY7C1019DV33-10ZSXI图片预览
型号: CY7C1019DV33-10ZSXI
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位( 128K ×8)静态RAM [1-Mbit (128K x 8) Static RAM]
分类和应用:
文件页数/大小: 11 页 / 387 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C1019DV33
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR [4]
t
R[13]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= V
DR
= 2.0V, CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
0
t
RC
Conditions
Min.
2.0
3
Max.
Unit
V
mA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
V
DR
>
2V
3.0V
t
R
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[14, 15]
t
RC
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[15, 16]
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
DATA OUT
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
ISB
ICC
HIGH
IMPEDANCE
Notes
13. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 50
µs
or stable at V
CC(min.)
> 50
µs.
14. Device is continuously selected. OE, CE = V
IL
.
15. WE is HIGH for Read cycle.
16. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05481 Rev. *D
Page 6 of 11