CY7C109B
CY7C1009B
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255Ω
R1 480Ω
R1 480Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
Equivalent to:
R2
255Ω
GND
≤
3 ns
3.0V
90%
10%
90%
10%
≤
3 ns
ALL INPUT PULSES
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Switching Characteristics
[5]
7C109B-12
7C1009B-12
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid, CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[6, 7]
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[7]
CE
1
HIGH to High Z, CE
2
LOW to High Z
[6, 7]
CE
1
LOW to Power-Up, CE
2
HIGH to Power-Up
CE
1
HIGH to Power-Down, CE
2
LOW to Power-Down
Write Cycle Time
[9]
CE
1
LOW to Write End, CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
12
10
10
0
0
10
7
0
3
6
0
12
15
12
12
0
0
12
8
0
3
7
3
6
0
15
20
15
15
0
0
12
10
0
3
8
0
6
3
7
0
20
3
12
6
0
7
3
8
12
12
3
15
7
0
8
15
15
3
20
8
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C109B-15
7C1009B-15
Min.
Max.
7C109B-20
7C1009B-20
Min.
Max.
Unit
Write Cycle
[8]
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. CE
1
and WE must be LOW and CE
2
HIGH to initiate a
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05038 Rev. *C
Page 3 of 10
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