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CY7C057V-12AC 参数 Datasheet PDF下载

CY7C057V-12AC图片预览
型号: CY7C057V-12AC
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 16K / 32K ×36 FLEx36异步双端口静态RAM [3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM]
分类和应用:
文件页数/大小: 23 页 / 461 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C056V
CY7C057V
Electrical Characteristics
Over the Operating Range
[7, 8]
CY7C056V
CY7C057V
-12
Max.
Min.
Min.
Typ.
Parameter
V
OH
V
OL
V
IH
V
IL
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
(V
DD
= Min., I
OH
= –4.0 mA)
Output LOW Voltage
(V
DD
= Min., I
OL
= +4.0 mA)
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
Operating Current (V
DD
= Max.,
I
OUT
= 0 mA) Outputs Disabled
Standby Current (Both Ports TTL
Level and Deselected)
f = f
MAX
Standby Current (One Port TTL
Level and Deselected)
f = f
MAX
Standby Current (Both Ports CMOS
Level and Deselected) f =0
Standby Current (One Port CMOS
Level and Deselected) f = f
MAX[9]
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
160 210
0.01
1
180 240
55
75
–10
2.0
0.8
10
250 385
–10
240
265
50
65
175
190
0.01
0.01
155
170
-15
Max.
Min.
Typ.
-20
Max.
0.4
2.0
0.8
10
360
385
70
95
230
255
1
1
200
215
0.01
1
45
65
–10
0.8
10
Unit
pF
pF
Typ.
Unit
V
V
V
V
µA
mA
mA
mA
165 210 mA
mA
mA
mA
145 180 mA
mA
2.4
0.4
2.4
0.4
2.0
2.4
230 340 mA
I
SB2
I
SB3
I
SB4
Capacitance
[10]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
DD
= 3.3V
Max.
10
10
Notes:
7. Cross Levels are V
DD
– 0.2V< V
Z
<0.2V.
8. Deselection for a port occurs if CE
0
is HIGH or if CE
1
is LOW.
9. f
MAX
= 1/t
RC
= All inputs cycling at f = 1/t
RC
(except Output Enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
standby I
SB3
.
10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06055 Rev. **
Page 6 of 23