CY7C056V
CY7C057V
Switching Characteristics
Over the Operating Range
[13]
(continued)
CY7C056V
CY7C057V
-12
Parameter
Busy Timing
[19]
t
BHC
t
PS
t
WB
t
WH
t
BDD[20]
t
INS
t
INR
t
SOP
t
SWRD
t
SPS
t
SAA
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W LOW after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
5
0
11
12
12
5
0
13
15
15
5
0
15
20
20
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-15
Max.
Min.
-20
Max.
Unit
Interrupt Timing
[19]
INT Set Time
INT Reset Time
12
12
15
15
20
20
ns
ns
Semaphore Timing
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
5
12
10
5
5
15
10
5
5
20
ns
ns
ns
ns
Data Retention Mode
The CY7C056V and CY7C057V are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within V
DD
to V
DD
– 0.2V.
2. CE must be kept between V
DD
– 0.2V and 70% of V
DD
during the power-up and power-down transitions.
3. The RAM can begin operation >t
RC
after V
DD
reaches the
minimum operating voltage (3.15 volts).
[3]
Timing
Data Retention Mode
V
CC
3.15V
V
CC
>
2.0V
3.15V
t
RC
V
IH
CE
V
CC
to V
CC
– 0.2V
Parameter
ICC
DR1
Test Conditions
[21]
@ VDD
DR
= 2V
Max.
50
Unit
µA
Notes:
20. t
BDD
is a calculated parameter and is the greater of t
WDD
–t
PWE
(actual) or t
DDD
–t
SD
(actual).
21. CE = V
DD
, V
in
= V
SS
to V
DD
, T
A
= 25
°
C. This parameter is guaranteed but not tested.
Document #: 38-06055 Rev. **
Page 10 of 23
CYPRESS [ CYPRESS SEMICONDUCTOR ]
