25/0251
CY7C056V
CY7C057V
3.3V 16K/32K x 36
FLEx36™ Asynchronous Dual-Port Static RAM
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• 16K x 36 organization (CY7C056V)
• 32K x 36 organization (CY7C057V)
• 0.25-micron CMOS for optimum speed/power
• High-speed access: 12/15/20 ns
• Low operating power
—
Active: I
CC
= 250 mA (typical)
— Standby: I
SB3
= 10
µA
(typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 72 bits or more using Mas-
ter/Slave Chip Select when using more than one device
• On-Chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Byte Select on Left Port
• Bus Matching on Right Port
• Depth Expansion via dual chip enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Compact package
— 144-Pin TQFP (20 x 20 x 1.4 mm)
—
172-Ball BGA (1.0-mm pitch) (15 x 15 x.51 mm)
Logic Block Diagram
R/W
L
B
0
–B
3
CE
0L
CE
1L
OE
L
9
R/W
R
Left
Port
Control
Logic
Right
Port
Control
Logic
9
9
CE
L
CE
R
CE
0R
CE
1R
OE
R
BA
WA
I/O
0L
–I/O
8L
9
I/O
9L
–I/O
17L
9
I/O
18L
–I/O
26L
9
I/O
Control
I/O
Control
9
9
Bus
Match
9/18/36
I/O
R
I/O
27L
–I/O
35L
BM
SIZE
A
0L
–A
13/14L
[1]
14/15
Address
Decode
14/15
True Dual-Ported
RAM Array
Address
Decode
14/15
14/15
A
0R
–A
13/14R
[1]
Interrupt
Semaphore
Arbitration
SEM
L
BUSY
L
INT
L
[2]
SEM
R
BUSY
R
INT
R
M/S
[2]
Notes:
1. A
0
–A
13
for 16K; A
0
–A
14
for 32K devices.
2. BUSY is an output in Master mode and an input in Slave mode.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06055 Rev. **
Revised September 7, 2001
CYPRESS [ CYPRESS SEMICONDUCTOR ]
