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CY7C028V-15AC 参数 Datasheet PDF下载

CY7C028V-15AC图片预览
型号: CY7C028V-15AC
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 32K / 64K X 16/18双端口静态RAM [3.3V 32K/64K x 16/18 Dual-Port Static RAM]
分类和应用:
文件页数/大小: 18 页 / 237 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C027V/028V
CY7C037V/038V
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)
[20, 21, 22]
t
RC
ADDRESS
t
OHA
DATA OUT
t
AA
DATA VALID
t
OHA
PREVIOUS DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)
[20, 23, 24]
CE and
LB or UB
OE
t
LZOE
DATA OUT
t
LZCE
t
PU
I
CC
CURRENT
I
SB
t
PD
DATA VALID
t
ACE
t
HZCE
t
DOE
t
HZOE
Read Cycle No. 3 (Either Port)
[20, 22, 23, 24]
t
RC
ADDRESS
t
AA
UB or LB
t
HZCE
t
LZCE
t
ABE
CE
t
ACE
t
LZCE
DATA OUT
t
HZCE
t
OHA
Notes:
20. R/W is HIGH for read cycles.
21. Device is continuously selected CE = V
IL
and UB or LB = V
IL
. This waveform cannot be used for semaphore reads.
22. OE = V
IL
.
23. Address valid prior to or coincident with CE transition LOW.
24. To access RAM, CE = V
IL
, UB or LB = V
IL
, SEM = V
IH
. To access semaphore, CE = V
IH
, SEM = V
IL
.
Document #: 38-06078 Rev. *A
Page 9 of 18