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CY7C028V-15AC 参数 Datasheet PDF下载

CY7C028V-15AC图片预览
型号: CY7C028V-15AC
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 32K / 64K X 16/18双端口静态RAM [3.3V 32K/64K x 16/18 Dual-Port Static RAM]
分类和应用:
文件页数/大小: 18 页 / 237 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
 浏览型号CY7C028V-15AC的Datasheet PDF文件第4页浏览型号CY7C028V-15AC的Datasheet PDF文件第5页浏览型号CY7C028V-15AC的Datasheet PDF文件第6页浏览型号CY7C028V-15AC的Datasheet PDF文件第7页浏览型号CY7C028V-15AC的Datasheet PDF文件第9页浏览型号CY7C028V-15AC的Datasheet PDF文件第10页浏览型号CY7C028V-15AC的Datasheet PDF文件第11页浏览型号CY7C028V-15AC的Datasheet PDF文件第12页  
CY7C027V/028V
CY7C037V/038V
Switching Characteristics
Over the Operating Range
[11]
(continued)
CY7C037V/038V
-15
Parameter
t
HD
t
HZWE[14, 15]
t
LZWE[14 ,15]
t
WDD[41]
t
DDD[41]
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD[18]
t
INS
t
INR
t
SOP
t
SWRD
t
SPS
t
SAA
Description
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
5
15
5
0
13
15
15
15
10
5
5
20
3
30
25
15
15
15
15
5
0
15
20
20
20
12
5
5
25
Min.
0
10
3
40
30
20
20
20
16
5
0
17
25
20
20
Max.
Min.
0
12
3
50
35
20
20
20
17
-20
Max.
Min.
0
15
-25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Busy Timing
[16]
Interrupt Timing
[16]
Semaphore Timing
Data Retention Mode
The CY7C027V/028V and CY7037V/038V are designed with
battery backup in mind. Data retention voltage and supply cur-
rent are guaranteed over temperature. The following rules en-
sure data retention:
1. Chip enable (CE) must be held HIGH during data retention, with-
in V
CC
to V
CC
– 0.2V.
2. CE must be kept between V
CC
– 0.2V and 70% of V
CC
during the power-up and power-down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the min-
imum operating voltage (3.0 volts).
Timing
Data Retention Mode
V
CC
3.0V
V
CC
>
2.0V
3.0V
t
RC
V
IH
CE
V
CC
to V
CC
– 0.2V
Parameter
ICC
DR1
Test Conditions
[19]
@ VCC
DR
= 2V
Max.
50
Unit
µA
16. For information on port-to-port delay through RAM cells from writing port
to reading port, refer to Read Timing with Busy waveform.
17. Test conditions used are Load 1.
18. t
BDD
is a calculated parameter and is the greater of t
WDD
–t
PWE
(actual) or t
DDD
–t
SD
(actual).
19. CE = V
CC
, V
in
= GND to V
CC
, T
A
= 25° C. This parameter is guaranteed
but not tested.
Document #: 38-06078 Rev. *A
Page 8 of 18