CY7C027V/028V
CY7C037V/038V
Switching Waveforms
(continued)
Busy Timing Diagram No. 1 (CE Arbitration)
[39]
CE
L
Valid First:
ADDRESS
L,R
CE
L
t
PS
CE
R
t
BLC
BUSY
R
t
BHC
ADDRESS MATCH
CE
R
Valid First:
ADDRESS
L,R
CE
R
t
PS
CE
L
t
BLC
BUSY
L
t
BHC
ADDRESS MATCH
Busy Timing Diagram No. 2 (Address Arbitration)
[39]
Left Address Valid First:
t
RC
or t
WC
ADDRESS
L
ADDRESS MATCH
t
PS
ADDRESS
R
t
BLA
BUSY
R
t
BHA
ADDRESS MISMATCH
Right Address Valid First:
t
RC
or t
WC
ADDRESS
R
ADDRESS MATCH
t
PS
ADDRESS
L
t
BLA
BUSY
L
t
BHA
ADDRESS MISMATCH
Note:
39. If t
PS
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Document #: 38-06078 Rev. *A
Page 13 of 18
CYPRESS [ CYPRESS SEMICONDUCTOR ]
