CY7C024/0241
CY7C025/0251
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR :
t
WC
ADDRESS
WRITE FFF (1FFF CY7C025)
[39]
L
t
HA
CE
L
R/W
INT
L
R
[40]
t
INS
7C024–27
Right Side Clears INTR:
t
RC
READ FFF
(1FFF CY7C025)
ADDRESS
R
CE
R
[40]
t
INR
R/W
R
OE
R
INT
R
7C024–28
:
Right SideSets INTL
t
WC
ADDRESS
WRITE FFE (1FFE CY7C025)
[39]
R
t
HA
CE
R
R
R/W
INT
L
[40]
INS
t
7C024–29
Left Side Clears INTL:
t
RC
READ FFE
(1FFE CY7C025)
ADDRESS
CE
R
L
[40]
t
INR
R/W
L
OE
INT
L
L
7C024–30
Notes:
39.
40.
t
t
depends on which enable pin (CE or R/W ) is deasserted first.
HA L L
or t depends on which enable pin (CE or R/W ) is asserted last.
INS
INR
L
L
Document #: 38-06035 Rev. *B
Page 14 of 20
CYPRESS [ CYPRESS ]
