CY7C024/0241
CY7C025/0251
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)[38]
CELValid First:
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
7C024–23
CER ValidFirst:
ADDRESS
ADDRESS MATCH
L,R
CE
R
t
PS
CE
L
L
t
t
BHC
BLC
BUSY
7C024–24
Busy Timing Diagram No.2 (Address Arbitration)[38]
Left Address Valid First
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
7C024–25
Right AddressValid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
7C024–26
Note:
38. If t is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
PS
Document #: 38-06035 Rev. *B
Page 13 of 20
CYPRESS [ CYPRESS ]
