CY7C024/0241
CY7C025/0251
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[33]
t
AA
t
OHA
A –A
0
VALID ADRESS
VALID ADRESS
2
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
SA
t
PWE
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
7C024–19
Timing Diagram of Semaphore Contention[34, 35, 36]
A
0L
–A
2L
MATCH
R/W
L
SEM
–A
L
t
SPS
A
MATCH
0R
2R
R/W
R
SEM
R
7C024–20
Notes:
33. CE = HIGH for the duration of the above timing (both write and read cycle).
34. I/O = I/O = LOW (request semaphore); CE = CE = HIGH.
0R
0L
R
L
35. Semaphores are reset (available to both ports) at cycle start.
36. If t is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
SPS
Document #: 38-06035 Rev. *B
Page 11 of 20
CYPRESS [ CYPRESS ]
