CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR :
t
WC
ADDRESS
WRITE 1FFF (OR 1/3FFF)
L
[48]
t
HA
CE
L
R/W
INT
L
R
[49]
t
INS
Right Side Clears INTR:
t
RC
READ 7FFF
(OR 1/3FFF)
ADDRESS
R
CE
R
[49]
t
INR
R/W
R
OE
R
INT
R
:
Right Side Sets INTL
t
WC
ADDRESS
WRITE 1FFE (OR 1/3FFE)
R
[48]
HA
t
CE
R
R
R/W
INT
L
[49]
INS
t
Left Side Clears INTL:
t
RC
READ 7FFE
OR 1/3FFE)
ADDRESS
R
CE
L
[49]
t
INR
R/W
L
OE
INT
L
L
Notes:
48.
49.
t
depends on which enable pin (CE or R/W ) is deasserted first.
HA L L
t
or t
depends on which enable pin (CE or R/W ) is asserted last.
L L
INS
INR
Document #: 38-06052 Rev. *H
Page 16 of 19
CYPRESS [ CYPRESS ]
