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CY7C024AV-20AXC 参数 Datasheet PDF下载

CY7C024AV-20AXC图片预览
型号: CY7C024AV-20AXC
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 4K / 8K / 16K X 16/18双端口静态RAM [3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM]
分类和应用:
文件页数/大小: 19 页 / 248 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Characteristics
Over the Operating Range (continued)
[19]
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
Parameter
t
SD
t
HD
t
HZWE[22, 23]
t
LZWE[22, 23]
t
WDD[24]
t
DDD[24]
Busy Timing
[25]
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD[26]
t
INS
t
INR
t
SOP
t
SWRD
t
SPS
t
SAA
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-up for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
5
20
5
0
15
20
20
20
12
5
5
25
20
20
20
17
5
0
17
25
20
20
20
20
20
17
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Data Set-up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
3
45
30
Min.
15
0
12
0
50
35
Max.
Min.
15
0
15
-25
Max.
Unit
ns
ns
ns
ns
ns
ns
Interrupt Timing
[25]
Semaphore Timing
Data Retention Mode
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV are designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within V
CC
to V
CC
– 0.2V.
2. CE must be kept between V
CC
– 0.2V and 70% of V
CC
during the power-up and power-down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the
minimum operating voltage (3.0V).
Timing
Data Retention Mode
V
CC
3.0V
V
CC
>
2.0V
3.0V
t
RC
V
IH
CE
V
CC
to V
CC
– 0.2V
Parameter
ICC
DR1
Test Conditions
[27]
@ VCC
DR
= 2V
Max.
50
Unit
μA
Notes:
24. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
25. Test conditions used are Load 2.
26. t
BDD
is a calculated parameter and is the greater of t
WDD
– t
PWE
(actual) or t
DDD
– t
SD
(actual).
27. CE = V
CC
, V
in
= GND to V
CC
, T
A
= 25°C. This parameter is guaranteed but not tested.
Document #: 38-06052 Rev. *H
Page 10 of 19