CY7B952
Electrical Characteristics
Over the Operating Range (continued)
Parameter
V
IHH
V
IMM
V
ILL
I
CCS
I
CCR
I
CCT
I
CCE
I
CC5
I
CCO
Description
Three-Level Input HIGH
Three-Level Input MID
Three-Level Input LOW
[5]
Test Condition
Min.
V
CC
−
0.75
V
CC
/2
−
0.5
0.0
Max.
V
CC
V
CC
/2 + 0.5
0.75
38
50
13
7.0
7.0
3
Unit
V
V
V
mA
mA
mA
mA
mA
mA
Three-Level Input Pins (MODE)
Operating Current
Static Operating Current
Receiver Operating Current
Transmitter Operating Current
ECL Pair Operating Current
Additional Current at 51.84 MHz
Additional Current LFI=LOW
Capacitance
[6]
Parameter
C
IN
Description
Input Capacitance
Test Conditions
T
A
= 25°C, f
0
= 1 MHz, V
CC
= 5.0V
Max.
10
Unit
pF
AC Test Loads and Waveforms
5V
OUTPUT
R1=910Ω
R2=510Ω
C
L
< 30 pF
(Includes fixture and
probe capacitance)
C
L
R2
R1
C
L
R
L
V
CC
– 2
R
L
=50Ω
C
L
< 5 pF
(Includes fixture and
probe capacitance)
[7]
(a) TTL AC Test Load
3.0V
3.0V
2.0V
GND
< 1 ns
1.0V
2.0V
[7]
(b) ECL AC Test Load
V
IHE
80%
V
ILE
20%
V
IHE
80%
20%
V
ILE
< 1 ns
1.0V
< 1 ns
< 1 ns
(c) TTL Input Test Waveform
(d) ECL Input Test Waveform
Switching Characteristics
Over the Operating Range
Parameter
f
REF
f
B
t
ODC
t
RF
t
LOCK
Reference Frequency
Bit
Time
[8]
[6]
Description
MODE=LOW
MODE=HIGH
MODE=LOW
MODE=HIGH
Output Duty Cycle (TCLK±, RCLK±)
Output Rise/Fall Time
[6]
PLL Lock Time (RIN transition density 25%)
[9]
Min.
6.41
19.24
19.5
6.50
48
0.4
Max.
6.55
19.64
19.1
6.40
52
1.2
3
Unit
MHz
MHz
ns
ns
%
ns
ms
Notes:
5. Total Receiver operating current (assuming that the Transmitter is not activated) can be found by adding I
CCS
+ I
CCR
+ x * I
CCE
; where x is 2 if the ROUT± outputs
are not activated and 3 if they are activated. Total Transmitter operating current (assuming that the Receiver is not activated) can be found by adding I
CCS
+ I
CCT
+ x * I
CCE
; where x is 1 if the TOUT± outputs are not activated and 2 if they are activated. Total device power (assuming that the Transmitter and the Receiver
are activated) can be found by adding I
CCS
+ I
CCR
+ I
CCT
+ x * I
CCE
; where x represents the number of ECL output pairs activated.
6. Tested initially and after any design or process changes that may affect these parameters.
7. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
8. f
B
is calculated a 1/(f
REF×8
).
9. t
LOCK
is the time needed for transitioning from lock to REFCLKx8 to lock to data.
Document #: 38-02018 Rev. *B
Page 6 of 9
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