CY7B952
SST™ SONET/SDH Serial Transceiver
Features
• OC-3 Compliant with Bellcore and CCITT (ITU) specifi-
cations on:
— Jitter Generation (<0.01 UI)
— Jitter Transfer (<130 kHz)
— Jitter Tolerance
• SONET/SDH and ATM Compliant
• Compatible with IGT WAC013, IGT WAC413, and
PMC-Sierra PM5343
• Clock and data recovery from 51.84- or 155.52-MHz
datastream
• 155.52-MHz clock multiplication from 19.44-MHz source
• 51.84-MHz clock multiplication from 6.48-MHz source
•
±1%
frequency agility
• Line Receiver Inputs: No external buffering required
• Differential output buffering
• 100K ECL compatible I/O
• No output clock “drift” without data transitions
• Link Status Indication
• Loop-back testing
• Single +5V supply
• 24-pin SOIC
• Compatible with fiber-optic modules, coaxial cable, and
twisted pair media
• Power-down options to minimize power or crosstalk
• Low operating current: <70 mA
•
0.8µ BiCMOS
Functional Description
The SONET/SDH Serial Transceiver (SST) is used in
SONET/SDH and ATM applications to recover clock and data
information from a 155.52-MHz or 51.84-MHz NRZ or NRZI
serial data stream and to provide differential data buffering for
the Transmit side of the system.
Logic Block Diagram
FC+
FC–
RIN+
RIN–
LOOP(t)
MODE
Pin Configuration
SOIC
Top View
FC+
FC–
RIN+
RIN–
MODE
V
CC
CD
LOOP
REFCLK–
REFCLK+
TOUT–
TOUT+
1
2
3
4
5
6
7
8
9
10
11
12
CY7B952
24
23
22
21
20
19
18
17
16
15
14
13
PLL
RCLK+
RCLK–
RSER+
RSER–
LFI(t)
RECEIVE
TRANSMIT
CD
TOUT+
TOUT–
PLL
x8
TSER+
TSER–
TCLK+
TCLK–
RCLK–
RCLK+
RSER–
RSER+
LFI
V
CC
V
SS
V
CC
TCLK–
TCLK+
TSER+
TSER–
REFCLK+
REFCLK–
SST
Clock/Data
Recovery
Line
Driver
Cypress
CY7B952
S->P
SONET/SDH
Transport
Overhead
Transceiver
SONET/SDH
Path
Overhead
Transceiver
PMC-Sierra
PM5344SPTX
P->S
PMC-Sierra
PM5343STXC
Figure 1. SONET/SDH Overhead Processing Application
Cypress Semiconductor Corporation
Document #: 38-02018 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised April 27, 2004
CYPRESS [ CYPRESS SEMICONDUCTOR ]
