CY7B952
Pin Descriptions
(continued)
Name
MODE
I/O
3-Level In
Description
Frequency Mode Select.
This three-level input selects the frequency range for the clock and data
recovery Receive PLL and the frequency multiplier Transmit PLL. When this input is held HIGH the
two PLLs operate at the SONET (SDH) STS-3 (STM-1) line rate of 155.52 MHz. When this input is
held LOW the two PLLs operate at the SONET STS-1 line rate of 51.84 MHz. The REFCLK±
frequency in both operating modes is 1/8 the PLL operating frequency. When the MODE input is left
floating or held at V
CC
/2 the TSER± inputs substitute for the internal PLL VCO for use in factory
testing.
Power.
Ground.
The Transmit PECL differential input pair (TSER±) is buffered
by the SST yielding the differential data outputs (TOUT±).
These outputs can be used to directly drive transmission
media such as Printed Circuit Board (PCB) traces, optical
drivers, twisted pair, or coaxial cable.
Receive Functions
The primary function of the receiver is to recover clock
(RCLK±) and data (RSER±) from the incoming differential
PECL data stream (RIN±) without the need for external
buffering. These built-in line receiver inputs, as well as the
TSER± inputs mentioned above, have a wide common-mode
range (2.5V) and the ability to receive signals with as little as
50 mV differential voltage. They are compatible with all PECL
signals and any copper media.
The clock recovery function is performed using an embedded
PLL. The recovered clock is not only passed to the RCLK±
outputs, but also used internally to sample the input serial
stream in order to recover the data pattern. The Receive PLL
uses the REFCLK input as a byte-rate reference. This input is
multiplied by 8 (REFCLK×8) and is used to improve PLL lock
time and to provide a center frequency for operation in the
absence of input data stream transitions. The receiver can
recover clock and data in two different frequency ranges
depending on the state of the three-level MODE pin as
explained earlier. To insure accurate data and clock recovery,
REFCLK×8 must be within 1000 ppm of the transmit bit rate.
The standards, however, specify that the REFCLK×8
frequency accuracy be within 20–100 ppm.
The FC± pins are used to connect an external phase locked
loop damping capacitor and resistor. The capacitor should be
a 1
µF ±
10% surface mount devices and the resistor should
be a 301K
±
1% surface mount devices. To minimize noise, the
capacitor and the resistor should be placed on the SST side of
the printed circuit board as close to the FC± pins as possible.
The Receive PLL is compliant with the OC-3 Bellcore jitter
generation, jitter transfer, and jitter tolerance specifications.
Carrier Detect (CD) and Link Fault Indicator (LFI)
Functions
The Link Fault Indicator (LFI) output is a TTL-level output that
indicates the status of the receiver. This output can be used by
an external controller for Loss of Signal (LOS), Loss of Frame
(LOF), or Out of Frame (OOF) indications. LFI is controlled by
the Carrier Detect input, the internal Transitions Detector, and
the PLL Out of Lock (OOL) circuitry.
The CD input may be driven by external circuitry that is
monitoring the incoming data stream. Optical modules have
CD outputs that indicate the presence of light on the optical
Page 3 of 9
V
CC
V
SS
Description
The CY7B952 Serial SONET/SDH Transceiver (SST) is used
in SONET/SDH and ATM applications to recover clock and
data information from a 155.52-MHz or 51.84-MHz NRZ (Non
Return to Zero) or NRZI (Non Return to Zero Invert on ones)
serial data stream. This device also provides a bit-rate
Transmit clock, from a byte rate source through the use of a
frequency multiplier PLL, and differential data buffering for the
Transmit side of the system. This device is compliant with
relevant SONET/SDH specifications including OC-3 Bellcore
GR-253-Core Issue2, December 1995, ANSI T1X1.6/91-022,
and CCITT G958.
Operating Frequency
The SST operates at either of two frequency ranges. The
MODE input selects which of the two frequency ranges the
Transmit frequency multiplier PLL and the Receive clock and
data recovery PLL will operate. The MODE input has three
different functional selections. When MODE is connected to
VCC, the highest operating range of the device is selected. A
19.44-MHz
±1%
source must drive the REFCLK input and the
two PLLs will multiply this rate by 8 to provide output clocks
that operate at 155.52 MHz
±1%.
When the MODE input is
connected to ground (GND), the lowest operating range of the
device is selected. A 6.48-MHz
±1%
source must drive the
REFCLK inputs and the two PLLs will multiply this rate by 8 to
provide output clocks that operate at 51.84 MHz
±1%.
When
the MODE input is left unconnected or forced to approximately
V
CC
/2, the device enters Test mode.
Transmit Functions
The transmit section of the SST contains a PLL that takes a
REFCLK input and multiplies it by 8 (REFCLK×8) to produce
a PECL (Pseudo ECL) differential output clock (TCLK±). The
transmitter has two operating ranges that are selectable with
the three-level MODE pin as explained above. The SST
Transmit frequency multiplier PLL allows low-cost byte rate
clock sources to be used to time the upstream serial data
transmitter.
The REFCLK± input can be configured three ways. When both
REFCLK+ and REFCLK– are connected to a differential
100K-compatible PECL source, the REFCLK input will behave
as a differential PECL input. When either the REFCLK– or the
REFCLK+ input is at a TTL LOW, the other REFCLK input
becomes a TTL-level input allowing it to be connected to a
low-cost TTL crystal oscillator. The REFCLK input structure,
therefore, can be used as a differential PECL input, a single
TTL input, or as a dual TTL clock multiplexing input.
Document #: 38-02018 Rev. *B
CYPRESS [ CYPRESS SEMICONDUCTOR ]
