CY7B951
AC Test Loads and Waveforms
(a) TTL AC Test Load
(b) ECL AC Test Load
(c) TTL Input Test Waveform
(d) ECL Input Test Waveform
Switching Characteristics
Over the Operating Range
Parameter
f
REF
f
B
t
PE
t
ODC
t
RF
t
LOCK
t
RPWH
t
RPWL
t
DV
t
DH
t
PD
Reference Frequency
Bit Time
Receiver Static Phase
Error
Description
MODE = LOW
MODE = HIGH
MODE = LOW
MODE = HIGH
MODE = LOW
MODE = HIGH
Output Duty Cycle (TCLK±, RCLK±)
Output Rise/Fall Time
PLL Lock Time (RIN transition density 25%)
REFCLK Pulse Width HIGH
REFCLK Pulse Width HIGH
Data Valid
Data Hold
Propagation Delay (RIN to ROUT, TSER to TOUT)
10
10
3
1
10
48
0.4
Min.
6.41
19.24
19.5
6.50
Max.
6.55
19.64
19.1
6.40
100
200
52
1.2
100
Unit
MHz
MHz
ns
ns
ps
ps
%
ns
µs
ns
ns
ns
ns
ns
Notes
7. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
8. f
B
is calculated as 1/(f
REF
X8).
9. t
LOCK
is the time needed for transitioning from lock to REFCLK X8 to lock to data.
10. The ECL switching threshold is the differential zero crossing (i.e., the place where + and – signals cross).
Document Number: 38-02010 Rev. *A
Page 7 of 10
CYPRESS [ CYPRESS SEMICONDUCTOR ]
