CY7B923
CY7B933
Receiver Switching Characteristics Over the Operating Range (continued)[7]
7B933-155
7B933
7B933-400
Parameter
tCPXH
Description
REFCLK Clock Pulse HIGH
Min.
6.5
Max
Min.
Max.
Min.
6.5
Max. Unit
6.5
6.5
ns
ns
tCPXL
REFCLK Clock Pulse LOW
6.5
6.5
tDS
Propagation Delay SI to SO (note PECL and TTL
thresholds)[26]
20
20
20
ns
tSA
Static Alignment[13, 27]
100
100
100
ps
tEFW
Error Free Window[13, 28]
0.9tB
0.9tB
0.9tB
Switching Waveforms for the CY7B923 HOTLink Transmitter
t
CKW
t
CPWH
t
CPWL
CKW
ENA
t
SENP
t
HENP
t
SD
16,17
NOTES
D –D ,
0
7
SC/D,
SVS,
VALID DATA
BISTEN
t
t
HD
SD
DISABLED
ENABLED
t
PDF
RP
t
PDR
t
PPWH
t
CKW
t
CPWH
t
CPWL
CKW
t
t
HD
SD
ENN
D –D ,
0
7
SC/D,
SVS,
VALID DATA
BISTEN
t
t
HD
SD
Notes:
26. The PECL switching threshold is the midpoint between the PECL− V , and V specification (approximately V − 1.35V). The TTL switching threshold is 1.5V.
OH
OL
CC
27. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in 3,000
nominal transitions until a byte error occurs.
28. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured
over the operating range, input jitter < 50% Dj.
Document #: 38-02017 Rev. *E
Page 29 of 33
CYPRESS [ CYPRESS ]
